1. Field of the Invention
The invention relates to a method for fabricating a semiconductor device and, more specifically, to a method for fabricating a semiconductor device having a trench isolation layer.
2. Related Technology
General device isolation layers serve to insulate adjacent devices from each other. In particular, trench isolation layers are currently used. Methods for forming the trench isolation layers are well-known in the art. For example, as shown in FIG. 1A, a pad oxide layer and a pad nitride layer are sequentially formed on a substrate 100. Then, the resulting structure is subjected to patterning using a hard mask layer pattern, to form a structure in which a pad oxide pattern 110 and a pad nitride pattern 120 are sequentially laminated, in this order. A trench isolation region in the surface of the substrate 100, on which a trench isolation layer is to be formed, is exposed through the pad oxide pattern 110 and the pad nitride pattern 120. An exposed region of the substrate 100 is etched to a predetermined depth, to form a trench 130. Side walls of the trench 130 are damaged during the etching. Accordingly, in order to repair the etching damage, a side wall oxide layer 140 is formed, and a liner nitride layer 150 is then formed on the side wall oxide layer 140.
Next, as shown in FIG. 1B, a nitride layer 160 is formed such that the trench 130 is filled with the nitride layer 160, and the hard mask layer pattern is removed, thereby exposing the surface of the pad nitride pattern 120. The exposed pad nitride pattern 120 and the pad oxide layer pattern 110 are sequentially removed. The removal of the hard mask layer pattern to expose the surface of the pad nitride pattern 120 is carried out by chemical mechanical polishing (CMP). Also, the removal of the pad nitride layer pattern 120 is carried out by wet etching using a phosphorus solution.
In the process of forming a trench isolation layer, as described above, the substrate 100 may include a dummy region and a cell region. The dummy region corresponds to a wafer peripheral portion. In some cases, the dummy region may be an incompletely polished region after CMP, rather than the wafer peripheral portion. When the CMP is conducted to remove the hard mask layer pattern, the wafer peripheral portion tends to be polished incompletely, as compared to a wafer central portion. This is the reason that the size of a dummy pattern formed in the dummy region is relatively larger than that of a cell pattern formed in the cell region, and the CMP is made based on the cell pattern. Accordingly, the surface of the pad nitride layer pattern 120 in the cell region is exposed by CMP, but the surface of the pad nitride layer pattern 120 in the dummy region may not be exposed by CMP. As a result, in the dummy region, the sidewall oxide layer 140 may remain on the pad nitride layer pattern 120 after the CMP. When the sidewall oxide layer 140 remains on the pad nitride layer pattern 120, the pad nitride layer pattern 120 may not be removed due to the presence of the sidewall oxide layer 140 during the subsequent wet etching for removal of the pad nitride layer pattern 120.